1) Field of the Invention
This invention relates to a digital filter and an oversampling analog to digital converter which employs the digital filter.
2) Description of the Related Art
Analog data which are generally obtained in the fields of geophysical explorations, medical equipments or measurement instruments are processed by analog to digital conversion (A/D conversion), and digital time series data obtained as an output of the analog to digital conversion are processed by data processing after they are processed by filtering processing.
In this instance, when digital time series data are processed by low-pass filtering processing using plurality of cut-off frequencies, it is required that the cut-off characteristics be similar to each other.
As such analog to digital converter, for example, oversampling analog to digital converters have conventionally been developed which include a combination of a .DELTA..SIGMA. modulator and a decimation filter (digital low-pass filter which thins out data making use of a digital filter of the FIR type).
By the way, a digital filter of the FIR type which is used as a decimation filter is a digital filter whose impulse response has a definite length and which performs convolution calculation using a tap coefficient and input data to effect filtering processing. Such digital filter of the FIR type is shown in model diagram in FIG. 33 and in block diagram in FIG. 34.
Referring to FIGS. 33 and 34, in the digital filter of the FIR type shown, reference characters 1-0 to 1-(N-1) (N is a natural number) denote each a delay circuit for one clock time, 2 and 2-0 to 2-N denote each a multiplier, 3 and 3' denote each an adder, reference character 4 denotes an accumulator (accumulation means), reference characters 5 and 6 denote each a multiplexer, reference character 7 denotes coefficient vector setting means, 8 pointer means, and 9 a gate.
In the digital filter of the FIR including the components described above, the pointer means 8 outputs a common control signal P to the multiplexers 5 and 6 so that they successively output input signals thereto. Consequently, the multiplexers 5 and 6 successively output an input X(i) (i=0 to N) and a corresponding coefficient vector H(i), and the outputs of them are multiplied by each other by the multiplier 2 (2-i). A result of the multiplication and accumulation information of the accumulator 4 are added to each other by the adder 3 or 3', and a result of the addition is accumulated as the accumulation information in the accumulator 4 so as to allow such convolution calculation to be repeated subsequently. After such product sum calculation is repeated by N+1 times, the gate 9 is opened so that an output Y (=.SIGMA.H(i).multidot.X(i)) of the gate 9 is outputted as an output of the digital filter of the FIR type.
By the way, in order to vary the cut-off frequency among fc, 2xfc, 3xfc, . . . , Nxfc in digital low-pass filtering processing performed by such a decimation filter as described above, it is a common practice to prepare, as shown in FIG. 35, filter banks 7-1, . . . , 7-N in which different coefficient vectors corresponding to the individual cut-off frequencies are stored in advance so that a desired filter bank 7-i may be selected in accordance with the necessity to select a necessary coefficient vector.
Meanwhile, as a low-pass filter (for thinning out of conversion data) of the FIR type for use with an oversampling analog to digital converter, half band filters (HBFs) 10-1, 10-2, . . . , 10-N which are connected in cascade connection (tandem connection) in order to allow variation of the cut-off frequency are used as shown in FIG. 36. It is to be noted that reference characters 11-1, 11-2, . . . , 11-N denote each a decimator, and reference character f denotes a sampling rate.
By the way, when analog to digital conversion is performed, a gain error is produced. The gain error can be corrected using, as shown in FIG. 37, a divider 12 which divides an output value of a digital filter by a correction value set to a correction value register (REG) 13.
More particularly, referring to FIG. 37, when two arbitrary values (normally a positive (+) full scale and a negative (-) full scale, here, represented by I1 and I2, respectively) are inputted to the input of the digital filter, then values obtained by filtering processing are outputted from the digital filter. In this instance, from the input values I1 and I2 and output values O1 and O2, the ratio EQU (02-01)/(I2-I1) (1)
is calculated and stored into the correction register 13. Thereafter, the output of the filter can be divided by the data stored in the correction register 13 to obtain a value for which the gain error has been corrected.
Such correction, however, is conventionally performed using a divider or a like element outside such digital filter.
With the digital filter of the FIR type described above, however, when the filter banks are used for ordinary digital low-pass filtering processing, they must have coefficient vectors corresponding to individual cut-off frequencies. Accordingly, there is a subject to be solved in that, when it is tried to incorporate the digital filter into an LSI, a large number of gates are required and the efficient is low.
Meanwhile, the cascade connection (tandem connection) construction of half band filters for use for oversampling analog to digital conversion (thinning out of conversion data) only allows thinning out of 1/2.sup.N, and rounding processing of data is required at the output section of each stage.
Further, some filters are unnecessary depending upon the cut-off frequencies, and accordingly, the efficiency in use is low. As a possible solution to avoid the situation, a single filter may be used in a multiplexed condition. This, however, complicates the construction of a control circuit.
Accordingly, an FIR filter is demanded whose cut-off frequency can be varied with minimized number of filter coefficient vectors by a simple control circuit.
Further, the prior art digital filter requires a divider outside the same in order to correct a gain error produced upon analog to digital conversion. Thus, the prior art digital filter has a subject to be solved in that such requirement for a divider complicates the structure and complicates the calculation procedure.